1. Field of the Invention
The present invention relates to a flash memory device, and more particularly, to a floating gate of a flash memory device and a method for fabricating the same, that improves the yield and quality of a product.
2. Discussion of the Related Art
Generally, the size of a floating gate for building-up electrons is a very important factor in the process of fabricating a flash memory device having a size of 0.18 μm or less.
As the integration of flash memory devices improve, it is necessary to decrease an interval between adjacent floating gates. However, it is difficult to form a fine pattern in the flash memory device with a recent photolithography process. To overcome these problems, the floating gates are formed with an oxide spacer structure and a hard mask using oxide.
Hereinafter, a method for fabricating a floating gate of a flash memory device according to the related art will be described with reference to the accompanying drawings.
FIGS. 1A to 1E are cross sectional views showing a method for fabricating a floating gate of a flash memory device according to the related art.
As shown in FIG. 1A, a tunneling oxide layer 12 is formed having a thickness between 80 Å and 120 Å on a semiconductor substrate 11. Then, a polysilicon layer for a floating gate 13a is formed having a thickness between 900 Å and 1100 Å on the tunneling oxide layer 12.
Referring to FIG. 1B, a first oxide layer 14 is formed at a thickness between 2000 Å and 2500 Å on the polysilicon layer 13a. After coating a photoresist 15 on the first oxide layer 14, the photoresist 15 is selectively patterned by exposure and development, thereby defining a floating gate area.
In this case, after coating the photoresist 15, an anti-reflection layer (not shown) may be formed having a thickness of about 600 Å on the photoresist 15.
Subsequently, the first oxide layer 14 is selectively patterned using the patterned photoresist 15 as a mask.
As shown in FIG. 1C, after removing the photoresist 15, a cleaning process is performed to remove residual substances of the photoresist 15 from the semiconductor substrate 11.
Then, a second oxide layer is formed on an entire surface of the semiconductor substrate 11 including the first oxide layer 14, wherein the second oxide layer is formed at a thickness between 650 Å and 850 Å. After that, an etching-back process is applied to the entire surface of the second oxide layer. Accordingly, second oxide sidewalls 16 are formed at both sides of the first oxide layer 14.
As shown in FIG. 1D, the polysilicon layer 13a is selectively etched using the first oxide layer 14 and the second oxide sidewalls 16 as a mask, thereby forming a floating gate 13.
At this time, the floating gate 13 is larger in width than the floating gate area defined by the patterned photoresist 15.
As shown in FIG. 1E, the first oxide layer 14 and the second oxide sidewalls 16 are removed by wet-etching.
In the meantime, if spacers are patterned below 100 nm with the photoresist pattern provided on the polysilicon layer 13a, it is unnecessary to provide the hard mask process. However, it is difficult to form the fine pattern below 100 nm with the recent photo process. Accordingly, the fine pattern of 100 nm or less is formed with the hard mask such as the oxide layer.
After that, the oxide layer for the hard mask is removed by the wet-etching process. At this time, the yield is lowered and the quality of product is deteriorated due to many defects generated when performing the wet-etching process.